1. Field of Invention
The invention relates to a semiconductor integrated circuit that suspends operation of an interface circuit, which exchanges a signal with an external unit, in a non-access mode that an external access is not executed. More particularly, the invention is directed to a semiconductor integrated circuit including an interface circuit capable of receiving an external signal of a potential higher than a power supply voltage applied to the interface circuit.
2. Description of Related Art
In order to promote power saving in electronic devices, such as ICs and LSIs (semiconductor integrated circuit) for various electronic apparatuses, it is attempted to reduce power supply voltages to be supplied, and some electronic devices are driven with 3.3V or 3V (hereinafter also referred to as ‘3V group’) power supply voltages. Furthermore, others are driven with 1.8V or 1.5V (hereinafter referred to as ‘1V group’) power supply voltages.
However, not all electronic devices mounted in electronic apparatuses similarly employ such reduced power supply voltages. In some cases, an electronic device that operates with a 5V (hereinafter also referred to as ‘5V group’) power supply voltage of prior art and an electronic device that operates with the 3V group power supply voltage may be provided in a mixed manner.
Generally, a maximum rated voltage (also referred to as a ‘withstand voltage’) at a gate electrode of a transistor forming an electronic device which operates with the 3V group power supply voltage (hereinafter, simply referred to as ‘3V group electronic device’) is greater than the 3V group power supply voltage. However, it is lower than a withstand voltage at a transistor forming an electronic device which operates with the 5V group power supply voltage (hereinafter, simply referred to as ‘5V group electronic device’), and also lower than a potential of a signal output from the 5V group electronic device (hereinafter referred to as ‘5V group signal’). This means that the 5V group signal cannot externally be input to the 3V group electronic device.
Thus, in order to solve this problem of the withstand voltage, as described below, it is conceived employing a method of allowing the 3V group electronic device to receive not only a signal output from the 3V group electronic device (hereinafter referred to as ‘3V group signal’), but also the 5V group signal.
FIG. 6 is an explanatory diagram illustrating an interface circuit capable of receiving both the 3V group and 5V group signals. As shown in FIG. 6(A), this interface circuit includes an external input terminal (pad) PD and a transfer gate QTN (also referred to as ‘transmission gate’) including an n-type MOS transistor (hereinafter, also referred to as ‘NMOS transistor’) between the external input terminal PD and an input buffer 11B. Then, the 3V group voltage (3.3V in this example), the same as a power supply voltage supplied to the input buffer IB, is applied as a gate voltage VG to a gate electrode G of the transfer gate QTN.
As shown in FIG. 6(B), a potential VD of a drain electrode D of the transfer gate QTN is equal to a potential VPD of an input data signal to be input from the external input pad PD and varies in response to a change in the potential VPD. More specifically, when the potential VPD changes from 0V to 5V, the potential VD of the drain electrode D also changes from 0V to 5V. On the other hand, a potential VS of a source electrode S changes in response to a change in the potential VPD while the potential VPD is lower than a voltage, (VG−VTN)[V], which is lower than the gate voltage VG (=3.3V) by a threshold voltage VTN. However, the potential VS remains constant at (VG−VTN)[V] when the potential VPD is the (VG−VTN)[V] voltage or more. Therefore, in this interface circuit, the 5V type signal greater than the withstand voltage of the MOS transistor forming the input buffer IB is input from the external input pad PD through the transfer gate QTN, enabling the signal to be converted into a signal lower than the power supply voltage (3.3 V), and then input to the input buffer IB.
Moreover, when a signal potential of an external data signal input from the external input pad PD is 5V, the drain voltage VD applied to the drain electrode D of the transfer gate QTN is 5V. Therefore, a voltage VDG between the drain electrode D and the gate electrode G of the transfer gate QTN is 1.7V. Furthermore, when a signal potential of an external data signal input from the external input pad PD is 0V, the drain voltage VD applied to the drain electrode D of the transfer gate QTN is 0V. Therefore, the voltage VDG between the drain and the gate of the transfer gate QTN is −3.3V. Here, used as an MOS transistor regularly used in a circuit which operates with the 3.3V group power supply voltage may be an MOS transistor in which at least the maximum rated voltage (withstand voltage) allowable for the gate electrode is greater than the power supply voltage 3.3V, and also the maximum rated voltage allowable as the voltage between the drain and the gate is greater than the power supply voltage 3.3V. Therefore, this reveals that the voltage applied between the drain electrode and the gate electrode of the transfer gate QTN is lower than the maximum rated voltage.